Test Release

Web Address

Current Status

MASE

http://www.eecs.umich.edu/~taustin/code/mase-test1.tar.gz

http://www.eecs.umich.edu/~taustin/code/ANNOUNCE-mase.txt

The MASE code is stable, documentation is included in the test distribution, the code is awaiting integration into the main SimpleScalar 4.0 code base.  A report on the MASE microarchitecture simulation infrastructure is available here.  Details on the latest version of MASE and updates are contained in the release documentation.

SimpleScalar/ARM

http://www.eecs.umich.edu/~taustin/code/arm/ANNOUNCE.ARM

http://www.eecs.umich.edu/~taustin/code/arm/simplesim-arm-0.2.tar.gz

The ARM target is stable and in heavy use at UM and many other institutions, the code is awaiting integration into the main SimpleScalar 4.0 code base.

SimpleScalar/ARM cross compiler kit

http://www.eecs.umich.edu/~taustin/code/arm-cross/ANNOUNCE.cross

http://www.eecs.umich.edu/~taustin/code/arm-cross/gcc-2.95.2.tar.gz

http://www.eecs.umich.edu/~taustin/code/arm-cross/binutils-2.10.tar.gz

http://www.eecs.umich.edu/~taustin/code/arm-cross/glibc-2.1.3.tar.gz

The ARM cross compiler is based on GNU GCC and the BINUTILS tool chain.  This code is stable.

MiBench embedded benchmark suite

http://www.eecs.umich.edu/mibench

MiBench code is stable, a report describing the benchmarks with initial performance analyses is included in the release.

PowerAnalyzer ARM power model

http://www.eecs.umich.edu/~jringenb/power/

Version 0.9 test release of the ARM power models, includes the latest version of SimpleScalar/ARM, these models have been validated against the UM MARS processor pipeline, validation against the SA-1110 and Xscale 80200 is ongoing.

Sim-Alpha 21264 validated model

http://www.cs.utexas.edu/~cart/code/alphasim-1.0.tgz

Version 1.0 of the Alpha 21264 microarchitecture model, stable and currently in use at multiple institutions.  Microbenchmarks use during validation are here, and a report detailing the model and its validation is here.

Ss-viz Visualization Tool

http://www.cs.utexas.edu/users/cart/code/ss-viz.tgz

ss-viz provides a graphical user interface to release 3.0a of sim-outorder, enabling users to step through program execution and view timing statistics at arbitrary cycles. It has been ported to and tested on Linux x86 and Solaris/Sparc. The README describes how to build and configure the tool.

Ss-PPC PowerPC target

http://www.cs.utexas.edu/users/cart/code/ss-ppc-big.tgz

http://www.cs.utexas.edu/users/cart/code/ss-ppc-little.tgz

The PowerPC instruction definition file and augmented timing simulator have been tested extensively on Linux/x86, Solaris/SPARC, and AIX/PowerPC platforms. Access ss-ppc-little for the Linux/x86 version, and ss-ppc-big for the Solaris and AIX versions. Most PowerPC instructions have been implemented, with the exception of some privileged instructions that will be incorporated in future releases. ss-ppc-little currently supports a greater number of system calls. Documentation is available in the ss-ppc tech report.

Ss-OS Full System PowerPC target

To appear…

GPV Graphical Pipeline Viewer

To appear…